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S3C72C8/p72c8 product overview 1 - 1 1 product overview overview the S3C72C8 single-chip cmos microcontroller has been designed for high performance using samsung's newest 4 -bit cpu core, sam47 (samsung arrangeable microcontrollers). with an up-to- 96 -d ot lcd direct drive capability flexible 16 -bit timer/counter, and 4-chanel comparator, t he S3C72C8 offers an excellent design solution for a low cd p and a card reader . up to 28 pins of the 44 -pin qfp or up to 26 pins of the 42-pin sdip package can be dedicated to i/o. eight vectored interrupts provide fast response to internal and external events. in addi tion, the S3C72C8 's advanced cmos technology pro vides for low power consumptio n. otp the S3C72C8 microcontroller is also available in otp (one time programmable) version, s3p72c8. s3p72c8 microcontroller has an on-chip 8k-byte one-time-programable eprom instead of masked rom. the s3p72c8 is comparable to S3C72C8, both in function and in pin configuration.
product overview s3 c72c8/p72c8 1 - 2 features memory ? 512 4-bit ram (including lcd display ram) ? 8 , 192 8-bit rom 28 i/o pins ? i/o: 26 pins (44-pin qfp, 42-pin sdip) ? output only: 2 pin s (44-pin qfp) lcd controller/driver ? 12 segments and 8 common terminals (3, 4, and 8 common selectable ) ? internal resistor circuit for lcd bias ? all dot can be switched on/off 8-bit basic timer ? 4 interval timer functions ? watch-dog timer 16 -bit timer/counter 1 ? programmable 16 -bit timer /counter ? arbitrary clock output ? external event counter ? external clock signal divider ? configurable as two 8-bit timer/counters ? serial i/o interface clock generator watch timer ? time interval generation: 0.5 s, 3.9 ms at 32768 hz ? four frequency outputs to buz pin ? clo ck source generation for lcd 8-bit serial i/o interface ? 8-bit transmit/receive mode ? 8-bit receive mode ? lsb-first or msb-first transmission selectable ? internal or external clock source comparator ? 4 channel mode: internal reference (4-bit resolution) ? 3 channel mode: external reference interrupts ? four internal vectored interrupts ? five external vectored interrupts ? two quasi-interrupts bit sequential carrier ? supports 16-bit serial data transfer in arbitrary format memory-mapped i/o structure ? data memory bank 15 power-down modes ? idle mode (only cpu clock stops) ? stop mode (main system oscillation stops) ? sub system clock stop mode oscillation sources ? crystal, ceramic, or rc for main system clock ? crystal oscillator for subsystem clock ? main system clock frequency: 0.4 mhz-6 mhz ? subsystem clock frequency: 32.768 k hz ? cpu clock divider circuit (by 4, 8, or 64) instruction execution times ? 0.67, 1.33, 10.7 s at 6 mhz (main) ? 0.95, 1.91, 15.3 s at 4.19 mhz (main) ? 122 s at 32.768 khz (subsystem) operating temperature ? ? 40 c to 85 c operating voltage range ? 1.8 v to 5.5 v package type ? 44-pin qfp, 42-pin sdip
S3C72C8/p72c8 product overview 1 - 3 block diagram 8-bit timer/ counter1a 8-bit timer/ counter1b com4-com7/ seg15-seg12 seg0-seg3/ p5.0-p5.3 seg4-seg7/ p6.0-p6.3 seg8-seg11/ p7.0-p7.3 com0-com3 program status word stack pointer arithmetic and logic unit instruction decoder internal interrupts interrupt control block instruction register program counter clock p3.0/intp30 p3.1/intp31 lcd driver/ controller 8 k byte program memory 512 x 4-bit data memory 44 qfp only 16-bit timer/ counter p2.0/cin0/k0 p2.1/cin1/k1 p2.2/cin2/k2 p2.3/cin3/k3 p5.0-p5.3/ seg0-seg3 p7.0-p7.3/ seg8-seg11 p4.0 p4.1 p6.0-p6.3/ seg4-seg7 reset xt out xt in x out x in watch timer basic timer watch dog timer i/o port 0 p0.0/ sck p0.1/so p0.2/si p0.3/btco sio comparator i/o port 1 p1.0/ tclo1/int0 p1.1/tcl1/int1 p1.2/clo/int2 p1.3/buz/int4 i/o port 2 i/o port 3 i/o port 6 i/o port 5 i/o port 7 output port 4 figure 1-1 . S3C72C8 simplified block diagram
product overview s3 c72c8/p72c8 1 - 4 pin assignments reset p0.3/btco p0.2/si p0.1/so p0.0/ sck p3.1/intp31 p3.0/intp30 seg0/p5.0 seg1/p5.1 seg2/p5.2 seg3/p5.3 com5/seg14 com6/seg13 com7/seg12 seg11/p7.3 seg10/p7.2 seg9/p7.1 seg8/p7.0 seg7/p6.3 seg6/p6.2 seg5/p6.1 seg4/p6.0 p2.0/cin0/k0 p2.1/cin1/k1 p2.2/cin2/k2 p2.3/cin3/k3 v dd v ss x out x in test xt in xt out S3C72C8 (44-qfp-1010b) 1 2 3 4 5 6 7 8 9 10 11 p4.0 p4.1 p1.3/buz/int4 p1.2/clo/int2 p1.1/tcl1/int1 p1.0/tclo1/int0 com0 com1 com2 com3 com4/seg15 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 figure 1-2 . S3C72C8 44- qfp pin assignment diagram
S3C72C8/p72c8 product overview 1 - 5 com1 com0 p1.0/tclo1/int0 p1.1/tcl1/int1 p1.2/clo/int2 p1.3/buz/int4 p2.0/cin0/k0 p2.1/cin1/k1 p2.2/cin2/k2 p2.3/cin3/k3 v dd v ss x out x in test xt in xt out reset p0.3/btco p0.2/si p0.1/so S3C72C8 (42-sdip-600) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 com2 com3 com4/seg15 com5/seg14 com6/seg13 com7/seg12 seg11/p7.3 seg10/p7.2 seg9/p7.1 seg8/p7.0 seg7/p6.3 seg6/p6.2 seg5/p6.1 seg4/p6.0 seg3/p5.3 seg2/p5.2 seg1/p5.1 seg0/p5.0 p3.0/intp30 p3.1/intp31 p0.0/ sck 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 figure 1-3. S3C72C8 42-sdip pin assignment diagram
product overview s3 c72c8/p72c8 1 - 6 table 1- 1. S3C72C8 pin descriptions pin name pin type description circuit type number share pin p0.0 p0.1 p0.2 p0.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test are possible. individual pins are software configurable as input or output; individual pins are software configurable as open-drain or push-pull output ; individual pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. e?1 16 (22) 15 (21) 14 (20) 13 (19) sck so si btco p1.0 p1.1 p1.2 p1.3 i /o same as port 0. e?1 39 (3) 40 (4) 41 (5) 42 (6) tclo1/int0 tcl1/int1 clo/int2 buz/int4 p2.0 p2.1 p2.2 p2.3 i/o same as port 0 except that port 2 is not configurable as n-channel open drain and is configurable as analog input pin. f?8 1 (7) 2 (8) 3 (9) 4 (10) k0/cin0 k1/cin1 k2/cin2 k3/cin3 p3.0 p3.1 i/o 2-bit i/o port 1-bit and 4-bit read/write and test is possible. individual pins are software configurable as input or output; individual pins are software configurable as open-drain or push-pull output; 2-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. e?3 18 (24) 17 (23) intp30 intp31 p4.0 p4.1 o 2-bit output port. 1-bit and 4-bit read/write and test is possible. individual pins are software configurable as open-drain or push-pull output. e-2 44 43 p5.0-p5.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. individual pins are software configurable as input or output; individual pins are software configurable as open-drain or push-pull output; 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. h-13 19-22 (25-28) seg0-seg3 p6.0-p6.3 i/o same as port5 h-13 23-26 (29-32) seg4-seg7 p7.0-p7.3 i/o same as port5 h-13 27-30 (33-36) seg8 -seg11
S3C72C8/p72c8 product overview 1 - 7 table 1- 1. S3C72C8 pin descriptions (continued) pin name pin type description circuit type number share pin seg0-seg3 i/o lcd segment display signal output pins h?13 19-22 (25-28) p5.0-p5.3 seg4-seg7 23-26 (29-32) p6.0-p6.3 seg8-seg11 27-30 (33-36) p7.0-p7.3 seg12-seg15 o lcd segment display output pins h?6 31-34 (37-40) com7-com4 com0 -com3 o lcd common signal output pins h?4 38-35 (2-1, 42-41) ? com4-com7 i/o lcd common signal output pins h?6 34-31 (40-37) seg 12? seg15 sck i/o serial interface clock signal e?1 16 (22) p0.0 so i/o serial data output e?1 15 (21) p0.1 si i/o serial data input e?1 14 (20) p0.2 btco i/o basic timer overflow signal e?1 13 (19) p0.3 tclo1 i/o timer/counter external clock output e?1 39 (3) p1.0/int0 tcl1 i/o timer/counter external clock input e?1 40 (4) p1.1/int1 clo i/o clock output e?1 41 (5) p1.2/int2 buz i/o frequency output to buzzer e?1 42 (6) p1.3/int4 reset i system reset pin b 12 (18) ? x in, x out ? clock input and output pins for main system clock ? 8-7 (14-13) ? xt in, xt out ? clock input and output pins for subsystem clock ? 10-11 (16-17) ? cin0?cin3 i analog input port for comparator f?8 1-4 (7-10) p2.0/k0 -p2.3/k3 k0?k3 i/o external interrupts. the triggering edge is selectable. f?8 1-4 (7-10) p2.0/cin0 -p2.3/cin3 int0 int1 i external interrupts. the triggering edge for int0 and int1 is selectable. e?1 39 (3) 40 (4) p1.0/tclo1 -p1.1/tcl1
product overview s3 c72c8/p72c8 1 - 8 table 1- 1. S3C72C8 pin descriptions (continued) pin name pin type description circuit type number share pin int2 i quasi-interrupt with detection of rising or falling edges. e-1 41 (5) p1.2/clo int4 i external interrupt with detection of rising or falling edges. e-1 42 (6) p1.3/buz intp30 intp31 i key scan interrupts inputs. e-3 18-17 (24-23) p3.0, p3.1 test i system test pin ? 9 (15) ? v dd ? power supply pin ? 5 (11) ? v ss ? ground pin ? 6 (12) ? notes: 1. parentheses indicate pin number for 42-sdip package. 2. pull-up resistors for all i/o ports are automatically disabled if they are configured to output mode.
S3C72C8/p72c8 product overview 1 - 9 pin circuit diagrams schmitt trigger input in v dd pull-up resistor figure 1-4. pin circuit type b v dd i/o p-ch output disable data v dd pull-up resistor pne pull-up resistor enable figure 1-5 . pin circuit type e-1
product overview S3C72C8/p72c8 1 - 10 v dd out data pne figure 1-6. pin circuit type e-2 pull-up resistor enable pne data circuit type e-4 v dd p-ch pull-up resistor ouput disable lcon.1 i/o figure 1-7 . pin circuit type e-3
S3C72C8/p72c8 product overview 1 - 11 v dd out data pne figure 1-8 . pin circuit type e-4 v dd com data v ss out lpot.3 v lc4 v lc1 figu re 1-9. pin circuit type h-4
product overview S3C72C8/p72c8 1 - 12 v lc2 seg/com data v ss v lc4 out lpot.3 v dd v lc3 v lc1 figu re 1-10. pin circuit type h-6
S3C72C8/p72c8 product overview 1 - 13 v dd seg data output disable v ss v lc3 v lc2 out figu re 1-11. pin circuit type h-7
product overview S3C72C8/p72c8 1 - 14 pull-up resistor enable pne output disable data circuit type e-4 v dd p-ch circuit type h-7 seg figu re 1-12. pin circuit type h-13
S3C72C8/p72c8 product overview 1 - 15 (analog) v dd output disable data i/o p-ch v dd pull-up resistor pull-up resistor enable external ref (p2.3 only) (digital) intk ref comparator digital or analog can be seleted by software. + - figu re 1-13. pin circuit type f-8
S3C72C8/p72c8 electrical data 15- 1 1 5 electrical data overview in this section, information on S3C72C8 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? abso lute maximum ratings ? d.c. electrical characteristics ? main system clock oscillator characteristics ? subsystem clock oscillator characteristics ? i/o capacitance ? comparator electrical characteristics ? a.c. electrical characteristics ? o perating voltage range stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request miscellaneous timing waveforms ? a .c timing measurement point s ? clock timing measurement at x in ? clock timing measurement at xt in ? tcl1 timing ? input timing for reset signal ? input timing for external interrupts and quasi-interrupts ? serial data transfer timing
electrical data S3C72C8/p72c8 15- 2 table 15- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i all i/o pins active ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o p in active ? 15 ma all i/o pins active ? 3 5 output current low i ol one i/o pin active + 30 (peak value) ma + 15 * total for ports 0, 2?9 + 100 (peak value) + 60 * operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c * the values for output current low ( i ol ) are calculated as peak value duty . table 15- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units input high v ih1 ports 0, 1, 2, 3, 5, 6, 7, reset 0. 8 v dd ? v dd v voltage v ih2 x in , x out , xt in , and xt out v dd ? 0. 1 v dd input low v il1 ports 0, 1, 2, 3, 5, 6, 7, reset ? ? 0. 2 v dd v voltage v il 2 x in , x out , xt in , and xt out 0. 1 output high voltage v oh v dd = 4.5 v to 5.5 v i oh = ? 1 m a ports 0, 1, 2, 3, 4, 5, 6, 7 v dd ? 1.0 ? ? v output low voltage v ol v dd = 4.5 v to 5.5 v i ol = 15 ma ports 0, 1, 2, 3, 4, 5, 6, 7 ? ? 2.0 v v dd = 1.8 v to 5.5 v i ol = 1.6 ma 0.4
S3C72C8/p72c8 electrical data 15- 3 table 15- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units input high leakage current i lih1 v i = v dd all input pins except those specified below for i lih2 ? ? 3 a i lih2 v i = v dd x in , x out , xt in , and xt out 20 input low leakage current i lil1 v i = 0 v all input pins except reset , x in , x out , xt in , and xt out ? ? ? 3 a i lil2 v i = 0 v x in , x out , xt in , and xt out ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 a output low leakage current i lol v o = 0 v all output pins ? ? ? 3 a pull-up resistor r l i v i = 0 v; v dd = 5 v ports 0-3, 5-7 expect reset 25 47 100 k w v dd = 3 v 50 95 200 r l 2 v i = 0 v; v dd = 5 v , reset 100 220 400 v dd = 3 v 200 450 800 lcd voltage dividing resistor r lcd ta = 25 c 60 80 100 k w | v lc1 -com i | voltage drop (i = 0? 7 v dc ? 15 a per common pin ? ? 120 mv | v lc1 -segx| voltage drop (x = 0? 15) v ds ? 15 a per segment pin ? ? 120 v lc 1 output voltage v lc 1 v dd = 1.8 v to 5.5 v , 1/5 bias lcd clock = 0 hz, v lc d = v dd 0.8 v dd ? 0.2 0.8 v dd 0.8 v dd + 0.2 v v lc 2 output voltage v lc 2 0.6 v dd ? 0.2 0.6 v dd 0.6 v dd + 0.2 v lc 3 output voltage v lc 3 0.4 v dd ? 0.2 0.4 v dd 0.4 v dd + 0.2 v lc 4 output voltage v lc 4 0.2 v dd ? 0.2 0.2 v dd 0.2 v dd + 0.2
electrical data S3C72C8/p72c8 15- 4 table 15- 2. d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units supply current ( 1 ) i dd1 ( 2 ) v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz ? 3.0 2.3 8.0 5.5 ma v dd = 3 v 10% 6.0 mhz 4.19 mhz 1.5 1.0 4.0 3.0 i dd2 ( 2 ) idle mode v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz 1.3 1.2 2.5 1.8 v dd = 3 v 10% 6.0 mhz 4.19 mhz 0.5 0.44 1.5 1.0 i dd3 ( 3 ) v dd = 3 v 10% 32 khz crystal oscillator ? 15 .0 30 a i dd4 ( 3 ) idle mode; v dd = 3 v 10% 32 khz crystal oscillator 5.0 15 i dd5 stop mode; v dd = 5 v 10% scmod = 0000b xt in = 0v 2.5 5 stop mode; v dd = 3 v 10% 0.5 3 v dd = 5 v 10% scmod = 0100b 0.2 3 v dd = 3 v 10% 0.1 2 notes: 1 . currents in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors, comparator, output port drive currents . 2 . data includes power consumption for subsystem clock oscillation. 3 . when the system clock control register, scmod, is set to 1001b, main system clock oscillation stop s and the subsystem clock is used. 4. every values in this table is measured when the power control register (pcon) is set to "0011b".
S3C72C8/p72c8 electrical data 15- 5 table 15- 3. main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v ) oscillator clock configuration parameter test condition min typ max units ceramic oscillator xin xout c1 c2 oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range ; v dd = 3.0 v. ? ? 4 ms crystal oscillator xin xout c1 c2 oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) v dd = 2. 7 v to 5 .5 v ? ? 10 ms v dd = 1.8 v to 5 .5 v ? ? 30 external clock xin xout x in input frequency (1) ? 0.4 ? 6.0 mhz x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns rc oscillator xin xout r frequency r = 25 k w , v dd = 5 v ? 2 ? mhz r = 40 k w , v dd = 3 v ? 1 ? notes: 1. oscillation frequency and x in i nput frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
electrical data S3C72C8/p72c8 15- 6 table 15-4 . recommended oscillator constants (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v ) manufacturer series number (1) frequency range load cap (pf) oscillator voltage range (v) remarks c1 c2 min max tdk fcr ? e ? m5 3.58 mhz?6.0 mhz 33 33 2.0 5.5 leaded type fcr ? e ? mc5 3.58 mhz?6.0 mhz (2) (2) 2.0 5.5 on-chip c leaded type ccr ? e ? mc3 3.58 mhz?6.0 mhz (3) (3) 2.0 5.5 on-chip c smd type note s: 1. please specify normal oscillator frequency. 2. on-chip c: 30pf built in. 3. on-chip c: 38pf built in. table 15-5 . subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v ) oscillator clock configuration parameter test condition min typ max units crystal oscillator xtin xtout c1 c2 oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 2.7 v to 5.5 v ? 1.0 2 s v dd = 1.8 v to 5 .5 v ? ? 10 external clock xtin xtout xt in input frequency (1) ? 32 ? 100 khz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interv al required for oscillating stabilization after a power-on occurs.
S3C72C8/p72c8 electrical data 15- 7 table 15-6 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf table 15-7 . comparator electrical characteristics (t a = ? 40 c + 85 c, v dd = 4.0 v to 5.5 v, v ss = 0 v) parameter symbol condition min typ max units input voltage range ? ? 0 ? v dd v reference voltage range vref ? 0 ? v dd v input voltage internal vcin1 ? ? ? 150 mv accuracy external vcin2 ? ? ? 150 mv input leakage current icin, iref ? ? 3 ? 3 m a
electrical data S3C72C8/p72c8 15- 8 table 15-8 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units instruction cycle time (note) t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 s v dd = 1.8 v to 5 .5 v 1.33 64 tcl1 input frequency f ti1 v dd = 2.7 v to 5.5 v 0 ? 1 .5 mhz v dd = 1.8 v to 5 .5 v 1 tcl1 input high, low width t tih1 , t til1 v dd = 2.7 v to 5.5 v 0.48 ? ? s v dd = 1.8 v to 5 .5 v 1.8 sck cycle time t kcy v dd = 2.7 v to 5.5 v ; input 800 ? ? ns output 650 v dd = 1.8 v to 5 .5 v ; input 3200 output 3800 sck high, low width t kh , t kl v dd = 2.7 v to 5.5 v ; input 325 ? ? ns output t kcy /2 ? 50 v dd = 1.8 v to 5 .5 v ; input 1600 output t kcy / 2 ? 150 si setup time to sck high t sik v dd = 2.7 v to 5.5 v ; input 100 ? ? ns v dd = 2.7 v to 5.5 v ; output 150 v dd = 1.8 v to 5.5 v ; input 150 v dd = 1.8 v to 5.5 v ; output 500 si hold time to sck high t ksi v dd = 2.7 v to 5.5 v ; input 400 ? ? ns v dd = 2.7 v to 5.5 v ; output 400 v dd = 1.8 v to 5.5 v ; input 600 v dd = 1.8 v to 5.5 v ; output 500 note: unless otherwise specified, instruction cycle time condition values assume a main system clock ( fx ) source.
S3C72C8/p72c8 electrical data 15- 9 table 15-8 . a.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units output delay for sck to so t kso v dd = 2.7 v to 5.5 v ; input ? ? 300 ns v dd = 2.7 v to 5.5 v ; output 250 v dd = 1.8 v to 5.5 v ; input 1000 v dd = 1.8 v to 5.5 v ; output 1000 interrupt input high, low width t inth , t intl int0 , int1, int2, int4, k0? k 3, intp30, intp31 10 ? ? s reset input low width t rsl input 10 ? ? s note: minimum value for int0 is based on a clock of 2t cy or 128 / fx as assigned by the imod0 register setting. cpu clock = 1/n x oscillator frequency (n = 4, 8, or 64) 1 2 3 4 5 6 7 supply voltage (v) 0.75 mhz 15.6 khz cpu clock 1.5 mhz 3.0 mhz main oscillator frequency (divided by 4) 6 mhz 1.8 1.05 mhz 4.2 mhz figure 15- 1. standard operating voltage range
electrical data S3C72C8/p72c8 15- 10 table 15-9. ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 10 a release signal set time t srel ? 0 ? ? s oscillator stabilization wait time (1) t wait released by reset ? 2 17 / fx ? ms released by interrupt ? (2) ? notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
S3C72C8/p72c8 electrical data 15- 11 timing waveforms execution of stop instruction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode operating mode data retention mode t srel t wait reset v dd figure 15-2. stop mode release timing when initiated by reset reset execution of stop instruction v dddr ~ ~ data retention mode v dd normal operating mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 15-3. stop mode release timing when initiated by interrupt request
electrical data S3C72C8/p72c8 15- 12 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 15-4 . a.c. timing measurement points (except for x in and xt in ) x in t xh t xl 1/fx v dd - 0.1 v 0.1 v figure 15-5 . clock timing measurement at x in xt in t xth t xtl 1/fxt v dd - 0.1 v 0.1 v figure 15-6 . clock timing measurement at xt in
S3C72C8/p72c8 electrical data 15- 13 tcl1 t tih t til 1/f ti 0.7 v dd 0.3 v dd figure 15-7 . tcl1 timing reset t rsl 0.2 v dd figure 15-8 . input timing for reset reset signal int0, 1, 2, 4 k0 to k3 intp30, intp31 t inth t intl 0.8 v dd 0.2 v dd figure 15-9 . input timing for external interrupts and quasi-interrupts
electrical data S3C72C8/p72c8 15- 14 output data input data sck t kh t kcy t kl 0.8 v dd 0.2 v dd t kso t si k t ksi 0.8 v dd 0.2 v dd si so figure 15- 1 0 . serial data transfer timing
S3C72C8/p72c8 mechanical data 1 6- 1 16 mechanical data overview this section contains the following information about the device package: ? package dimensions in millimeters ? pad diagram note : dimensions are in millimeters. 39.50 max 39.10 0 .2 0.50 0.1 1.78 (1.77) 0.51 min 3.30 0.3 3.50 0.2 5.08 max 42-sdip-600 0-15 1.00 0.1 0.25 + 0.1 - 0.05 15.24 14.00 0 .2 #42 #22 #21 #1 figure 16-1. 42-sdip-600 package dimensions
mechanical data S3C72C8/p72c8 1 6- 2 44-qfp-1010b #44 note : dimensions are in millimeters. 10.00 0.2 13.20 0.3 10.00 0.2 13.20 0.3 #1 0.35 + 0.10 - 0.05 0.80 (1.00) 0.10 max 0.80 0.20 0.05 min 2.05 0.10 2.30 max 0.15 + 0.10 - 0.05 0-8 figure 16-1. 44-qfp-1010b package dimensions
S3C72C8/p72c8 s3p72c8 otp 17- 1 17 s3p72c8 otp overview the s3p72c8 single-chip cmos microcontroller is the otp (one time programmable) version of the S3C72C8 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the s3p72c8 is fully compatible with the S3C72C8, both in function and in pin configuration. because of its simple programming requirements, the s3p72c8 is ideal for use as an evaluation chip for the S3C72C8. p2.0/cin0/k0 p2.1/cin1/k1 sdat /p2.2/cin2/k2 sclk /p2.3/cin3/k3 v dd /v dd v ss /v ss x out x in v pp /test xt in xt out s3p72c8 1 2 3 4 5 6 7 8 9 10 11 p4.0 p4.1 p1.3/buz/int4 p1.2/clo/int2 p1.1/tcl1/int1 p1.0/tclo1/int0 com0 com1 com2 com3 seg15/com4 44 43 42 41 40 39 38 37 36 35 34 com5/seg14 com6/seg13 com7/seg12 seg11/p7.3 seg10/p7.2 seg9/p7.1 seg8/p7.0 seg7/p6.3 seg6/p6.2 seg5/p6.1 seg4/p6.0 33 32 31 30 29 28 27 26 25 24 23 reset reset / reset btco/p0.3 si/p0.2 so/p0.1 sck/ p 0.0 intp31/p3.1 intp30/p3.0 p5.0/seg0 p5.1/seg1 p5.2/seg2 p5.3/seg3 12 13 14 15 16 17 18 19 20 21 22 figure 17-1. s3p72c8 44-qfp pin assignments
s3p72c8 otp S3C72C8/p72c8 17- 2 com1 com2 p1.0/tclo1/int0 p1.1/tcl1/int1 p1.2/clo/int2 p1.3/buz/int4 p2.0/cin0/k0 p2.1/cin1/k1 sdat /p2.2/cin2/k2 sclk /p2.3/cin3/k3 v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset reset / reset p0.3/btco p0.2/si p0.1/so s3p72c8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 com2 com3 com4/seg15 com5/seg14 com6/seg13 com7/seg12 seg11/p7.3 seg10/p7.2 seg9/p7.1 seg8/p7.0 seg7/p6.3 seg6/p6.2 seg5/p6.1 seg4/p6.0 seg3/p5.3 seg2/p5.2 seg1/p5.1 seg0/p5.1 p3.0/intp30 p3.1/intp31 p0.0/ sck 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 figure 17-2. s3p72c8 42-sdip pin assignments
S3C72C8/p72c8 s3p72c8 otp 17- 3 table 17-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p2.2 sdat 3 (9) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p2.3 sclk 4 (10) i/o serial clock pin. input only pin. test v pp (test) 9 (15) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 12 (18) i chip initialization v dd /v ss v dd /v ss 5/6 (11/12) i logic power supply pin. v dd should be tied to + 5 v during programming. note : parentheses indicate pin number for 42-sdip package. table 17-2. comparison of s3p72c8 and S3C72C8 features characteristic s3p72c8 S3C72C8 program memory 8 kbyte eprom 8 kbyte mask rom operating voltage (v dd ) 1.8 v to 5.5 v 1.8 v to 5.5 v otp programming mode v dd = 5 v, v pp (test)=12.5v pin configuration 44-qfp, 42-sdip 44-qfp, 42-sdip eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the s3p72c8, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 17-3 below. table 17-3. operating mode selection criteria v dd v pp (test) reg/mem address (a15-a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
s3p72c8 otp S3C72C8/p72c8 17- 4 table 17-4 . d.c. electrical characteristics (t a = - 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units supply current ( 1 ) i dd1 ( 2 ) v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz ? 3.0 2.3 8.0 5.5 ma v dd = 3 v 10% 6.0 mhz 4.19 mhz 1.5 1.0 4.0 3.0 i dd2 ( 2 ) idle mode v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz 1.3 1.2 2.5 1.8 v dd = 3 v 10% 6.0 mhz 4.19 mhz 0.5 0.44 1.5 1.0 i dd3 ( 3 ) v dd = 3 v 10% 32 khz crystal oscillator ? 15 .0 30 m a i dd4 ( 3 ) idle mode; v dd = 3 v 10% 32 khz crystal oscillator 5.0 15 i dd5 stop mode; v dd = 5 v 10% scmod = 0000b xt in = 0v 2.5 5 stop mode; v dd = 3 v 10% 0.5 3 v dd = 5 v 10% scmod = 0100b 0.2 3 v dd = 3 v 10% 0.1 2 notes: 1 . currents in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors, comparator, output port drive currents . 2 . data includes pow er consumption for subsystem clock oscillation. 3 . when the system clock control register, scmod, is set to 1001b, main system clock oscillation stops and the subsystem clock is used. 4. every values in this table is measured when the power control register (pcon) is set to "0011b".
S3C72C8/p72c8 s3p72c8 otp 17- 5 cpu clock = 1/n x oscillator frequency (n = 4, 8, or 64) 1 2 3 4 5 6 7 supply voltage (v) 0.75 mhz 15.6 khz cpu clock 1.5 mhz 3.0 mhz main oscillator frequency (divided by 4) 6 mhz 1.8 1.05 mhz 4.2 mhz figure 17-3 standard operating voltage range
s3p72c8 otp S3C72C8/p72c8 17- 6 notes

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